1. Field of the Invention
The invention generally relates to design of integrated circuits and more specifically to designing functional blocks within integrated circuits and connecting functional blocks both within and between integrated circuits.
2. Description of the Related Art
Within integrated circuit designs, configuration registers are used for a variety of purposes, typically where a function may need to be altered either by software or by testing hardware and software. These configuration registers typically provide inputs to logic within the circuit, and the value of the configuration register thereby has a direct effect on performance of the integrated circuit. In some integrated circuit or chipset designs, the number of configuration registers grows so large that routing the signals for these registers becomes burdensome or problematic. The configuration registers are typically expected to be unchanging during most operations of the integrated circuit, so high speed read and write access is not necessarily the most important consideration in the design of the configuration bits.
FIG. 2A illustrates a common scheme for distributing configuration bits, wherein Configuration BLOCK (Functional Block) 240 utilizes groups of configuration lines 250 to distribute configuration bits to BLOCK 210, BLOCK 220, and BLOCK 230. Each of BLOCK 210, BLOCK 220, and BLOCK 230 implement functions on a single integrated circuit.
FIG. 2B illustrates one specific prior art scheme for configuration bits, wherein each of the bits is stored in a flip-flop or other storage circuit in the Configuration BLOCK 240, and a line from each storage circuit is connected to the destinations for that bit, wherever they may be. One will appreciate that a rat""s nest of signal lines may quickly develop in the process of routing all of these signals, especially the signals with multiple endpoints. Further, static timing, power consumption and reliability all become more problematic as fanout increases for a node or as actual length of the signal wire increases.
FIG. 2C illustrates an alternative prior art scheme for configuration bits. In this scheme, each bit is stored in a storage circuit in the BLOCK which utilizes the value of the bit. However, this also necessitates some form of signal (illustrated here as Write Enable WE) to enable writing to each storage circuit at the appropriate time, and another signal (read enable, not shown) which enables reading the signal. Effectively, two levels of decoding come into play, one at the centralized configuration block and another at the local level which ensures that the proper signals get to the proper registers to either read or write as appropriate. This extra level of overhead in the circuit design can create severe negative impacts on the overall integrated circuit.
Additionally, bi-directional signals or busses come into play. A bi-directional bus introduces problems of reliability and testability. To insure reliability, the circuit must be designed to carefully avoid contention on the bi-directional signal line, and also requires safeguards against a floating or unconnected signal line inducing a false signal in a circuit coupled to the bi-directional signal line. Furthermore, testability of bi-directional lines is problematic as typical ATPG (Automated Test Program Generation) regimes require that no contention or floating of the bi-directional signal line occur in the test vectors.
A method and apparatus for a Configuration Ring is described. The method and apparatus include a method of communicating between functional blocks including originating a packet, passing the packet, decoding the packet, and utilizing the packet. The method and apparatus further include a communications network including a first master having a ring interface and a control, a first target having a ring interface and a control, a first ring connection coupling the ring interface of the first master to the ring interface of the first target, a second target having a ring interface and a control, the first ring connection for passing packets, and a second ring connection coupling the ring interface of the first target to the ring interface of the second target, the second ring connection for passing packets, and a third ring connection coupling the ring interface of the second target to the ring interface of the first master, the third ring connection for passing packets.
Additionally, the method and apparatus include a communications network including a first master, a first target, a second target, and a ring, the ring coupled to the first master, the ring coupled to the first target, and the ring coupled to the second target. Moreover, the method and apparatus include a system including a processor, a processor bus coupled to the processor, a data chip coupled to the processor bus, and an address chip coupled to the processor bus and coupled to the data chip, the address chip including a configuration ring, the configuration ring having a master, a first target and a second target, the master coupled through a ring to the first target, the first target coupled through the ring to the second target, the second target coupled through the ring to the master.